The RF design decision chain in order — material, transmission lines, placement, grounding, thermal, validation — with the tolerance and loss math that separates RF layout from digital habit.
RF PCB design is often taught as a bag of rules, but the rules decompose into a chain of decisions made in order: material first, because everything downstream is calculated against it; then transmission-line geometry, then placement and routing, then grounding and shielding, and finally the thermal and validation work that decides whether the first prototype is the last. This guide walks the chain, condensing the decisions that matter at each stage.
Dielectric constant sets trace geometry and signal velocity; dissipation factor sets how much of the signal arrives; CTE sets whether the board survives its own assembly. Above roughly 1 GHz, FR-4’s loss tangent starts taxing every millimeter of trace, which is why RF designs move to PTFE or ceramic-filled laminates — the RT/duroid 5880 end for the lowest loss, the hydrocarbon RO4000 series overview where processability matters. Choose the material with the loss budget at the top frequency, not the average one.
Every RF trace is a transmission line: microstrip on outer layers, stripline between planes, coplanar waveguide where shielding matters. Their impedances come from trace width, dielectric height and Dk, controlled through the standard controlled impedance design rules — with the twist that RF tolerance is often ±5% or tighter and drift matters as much as the mean. At mmWave the tolerance stack tightens further; the budgeting method is walked through in the 0.05 mm microstrip tolerance walkthrough.
Place the RF chain first — antenna at the board edge with a clean ground beneath, filters adjacent to the stages they serve, oscillators isolated from everything digital. Then route: short, direct, few or zero vias, bends at 45 degrees or curves, and spacing that respects coupling. Vias deserve special suspicion; the discipline of blind and buried via design exists largely to keep signal transitions short and stub-free. Keep return paths continuous, and never route an RF line across a plane split.
A continuous ground plane under every RF trace is the load-bearing wall of the whole design. Isolate RF, digital and power grounds where they must be isolated, tie them at one deliberate point, and use stitching vias generously along RF return paths. Shield sensitive nodes with grounded pours or cans, and decouple supply pins with values staggered across the frequency range. Most EMI failures in RF boards trace to a return-path interruption, not to insufficient shielding.
Power amplifiers turn watts into heat on millimeters of board. Thermal vias under the pad, thick copper, and low-CTE materials keep the junction in range; the power-amplifier-specific finish and stackup decisions are analyzed in the 4350B power RF analysis. Thermal design belongs in the material decision, because thermal conductivity varies by an order of magnitude across RF laminates.
Simulate the stackup and critical nets, then verify with hardware: coupon-based impedance measurement, VNA sweeps of the actual traces, and environmental conditioning if the board will see temperature extremes. The measurement sequence mirrors the high-frequency PCB testing workflow. A design that reaches production without a VNA measurement of its own transmission lines is a design still carrying unpriced risk.
Frequently Asked Questions
Because trace geometry, loss budget, via behavior and thermal strategy are all calculated from the laminate's Dk, Df and CTE. Changing material after layout means redoing every calculation the layout was based on.
±5% is the common commercial target; mmWave and high-Q filter work often demands better, with the budget walked through per-stage rather than asserted as a single number.
Ideally zero through the RF chain. Each via adds inductance and a potential stub; where a transition is unavoidable, blind or back-drilled structures keep the parasitics bounded.
VNA measurement of the fabricated transmission lines against the simulated S-parameters, backed by coupon impedance data — simulation validates intent, measurement validates the board.
Send your frequency, loss budget and stackup draft and we will return a design review with material options and impedance targets before layout begins.
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