The core layout discipline — stackup and reference planes, placement zoning, routing order, power integrity — plus the frequency boundary where standard rules hand off to RF practice.
Good PCB layout is mostly discipline, and the same handful of rules produces boards that route cleanly, pass EMC on the first or second try, and stay manufacturable for years. This guide collects those rules for general and digital layouts — the standard stack from stackup planning through placement, routing, power integrity and DFM — and marks the point where high-frequency designs break away from them.
Decide the layer count and stackup before placing a single component, because every later rule assumes it. A four-layer board with internal ground and power planes is the smallest respectable stack for anything with fast edges; more complex designs follow the multi-layer layer count design principles. Two rules are non-negotiable: every signal layer needs an adjacent reference plane, and that plane should be continuous under the traces that use it. A signal crossing a plane split has no defined return path, and the EMI story writes itself from there.
Placement determines routing quality before any trace exists. Group related circuits so their interconnects stay short, put decoupling capacitors at the power pins they serve, and separate the noisy sections — switching regulators, motors, relays — from the sensitive ones. Heat sources belong where airflow or copper area can deal with them, and heat-sensitive precision circuits belong away from both. Time spent on placement is repaid with interest at routing; time saved on placement is repaid as spaghetti.
Route the critical nets first: clocks, high-speed interfaces, analog references. Keep traces short and direct, use 45-degree bends, and give differential pairs constant spacing with matched lengths. For high-speed signals the geometry becomes the impedance, so trace width and spacing come from the calculator, not from habit — the working numbers are collected in our high-frequency wiring recommendations. Everything else routes last, on the layers the critical nets left alone.
A solid ground plane is the cheapest signal integrity there is; dedicated power planes or pour regions keep supply impedance low across the board. Connect planes with stitching vias wherever return currents change layers, and decouple each supply rail at its consumers. The relationship between plane design and impedance control is covered in the controlled impedance design rules. Boards that skimp here pass functional tests and fail EMC chambers months later.
The rules above carry a design to several hundred megahertz. Beyond that, every trace becomes a transmission line, plane breaks become radiators, and component placement becomes field management — a different rulebook, developed in the RF PCB design guidelines. Knowing where the boundary sits is itself a layout skill: the expensive mistakes are treating an RF board with digital habits, or burdening a digital board with RF paranoia.
Frequently Asked Questions
Four layers with internal ground and power planes. Two-layer boards force return paths through routed traces and make EMC compliance largely a matter of luck.
At the IC. Bulk capacitance belongs near the power entry; the fast, local charge reserve each IC draws from belongs millimeters from its power pins.
Decisively. Well-zoned placement makes most nets route themselves; poor placement produces crossings and loops that no amount of routing skill recovers.
Roughly when trace length approaches a tenth of the signal wavelength — practically, designs with edges faster than about 1 ns or carriers above a few hundred MHz need transmission-line treatment.
Send your design files and we will run a DFM pass covering stackup, placement and routing rules — with RF escalation flagged where the frequency demands it.
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