The five stages that decide whether a multilayer high-frequency board works, the failure each stage produces when it is run loosely, and the control that prevents it.
Multilayer high-frequency boards sit inside almost every advanced system built today: 5G radio units, aerospace payloads, high-speed computing networks and automotive radar. Each of those applications asks the same thing of the board, which is to carry a signal a long way without letting it degrade, and each of them makes that harder by pushing frequency up and geometry down. A multilayer build is where those demands are met or lost, because the layers that carry the signal are bonded together in a single high-temperature operation that cannot be undone.
That is why a multilayer lamination is unforgiving. A mistake in stack-up, registration or resin flow does not produce a board that fails one test; it produces a batch that fails the same way. This article works through the stages that must be controlled, in the order they occur, and what actually goes wrong at each one.
The behaviour of a multilayer board is decided before any copper is patterned, by the dielectric underneath it. Four properties carry most of the weight on a high-frequency build, and each one fails in a different way.
Dk measures how much electrical energy the insulator stores, and high-frequency signals are acutely sensitive to it. When Dk varies across a panel, the propagation velocity varies with it, and the result is phase distortion rather than a simple attenuation. The requirement is therefore not just a low Dk but a consistent one, which is why materials with a uniform construction are preferred over glass-weave laminates where the resin-rich and glass-rich regions behave differently. PTFE, ceramic-filled hydrocarbon and modified epoxy systems are the families normally considered.
Df measures how much of the signal the dielectric converts into heat. Higher Df means higher attenuation, and at gigahertz frequencies the difference between an ordinary laminate and a low-loss one is the difference between a usable link and an unusable one. For work in the GHz range and above, materials with a Df well below 0.005 are the starting point rather than an upgrade.
A multilayer board is a stack of dielectric layers and copper foil bonded together, and the two materials expand at different rates. When that difference is large, thermal cycling during soldering or in service builds internal stress at every interface, and the stress concentrates at the points where the structure is weakest: plated through-hole barrels and the bond between copper and substrate. Thermal compatibility is therefore a reliability requirement, not a finishing detail. The alignment and expansion problems that follow a mismatch are covered in this article on compression, alignment and expansion control.
PTFE-based materials absorb moisture, and absorbed water changes both Dk and Df, which is the same as changing the circuit. It also turns to steam in the lamination press. Controlling the production environment and baking panels before lamination is therefore part of the electrical process, not housekeeping.
The inner layers carry the signal, so their geometric accuracy sets the electrical accuracy of the finished board. Three controls matter.
Impedance depends on line width, dielectric thickness and Dk, so the line width has to be produced as drawn. High-frequency multilayer work commonly runs at 3/3 mil or finer, and the tolerance on those dimensions is typically held within ±10%. Achieving that repeatably is a matter of exposure quality and etch control rather than of the artwork. The relationship between those dimensions and the finished impedance is set out in these steps for impedance control in high-frequency manufacturing.
Etching removes copper vertically and laterally, which leaves a trapezoidal cross-section rather than the rectangular one the design assumed. The lateral loss is undercut, and it reduces the effective line width. Etchant speed, chemical concentration and spray pressure all influence it, and on fine-line high-frequency work the etch line is tuned to suppress undercut rather than to maximise throughput.
A rough copper surface bonds well to the dielectric, and it also increases skin-effect loss at high frequency, so the two requirements pull against each other. Very Low Profile and Extremely Low Profile reverse-treated foils give a smoother surface, and they are normally specified where loss is the binding constraint rather than adhesion or cost.
Lamination bonds the inner layer cores and the prepreg sheets into one solid board under heat and pressure. It is the step where most expensive failures originate, because defects created here are buried inside the finished panel. The stages that lead into and out of it are described in this guide to multilayer high-frequency PCB manufacturing.
The stack-up has to be calculated before the press cycle, including the type, number and arrangement of prepreg sheets. That calculation fixes the finished dielectric thickness, the resin content and how much resin will flow during the cycle, and since dielectric thickness is one of the three variables behind impedance, the stack-up is an electrical document rather than a mechanical one.
A single dust particle trapped between layers becomes a delamination or a blister, so the lamination area is held at a cleanliness level that would be unnecessary for FR-4. Registration is the second control. The alignment features on each inner layer have to line up precisely, because a layer-to-layer shift can short or open a fine line, and on high-frequency boards it also distorts the transmission line geometry.
The heating curve and the moment pressure is applied decide how the resin behaves. Ramp too quickly and the resin reacts violently, releasing volatiles that become blisters. Apply pressure at the wrong point and the resin flows unevenly, which leaves uncontrolled thickness or shifted layers. The correct cycle is developed for the specific prepreg being used, not inherited from the previous build.
High-frequency multilayer boards tend to be thin with many layers, which makes them more prone to shifting during the cycle. Registration systems and resin flow channel design are the countermeasures. The other issue is residue: resin that flows into the gaps between circuits can interfere with the drilling and plating that follow, so the flow has to be controlled rather than merely tolerated.
Plated through-holes are the bridges between layers, and their quality decides the interconnection reliability of the whole board. The three stages below are the accepted process standard for low-loss multilayer work, and the same sequence applies on low-loss microwave PCB production more generally.
High-frequency materials, and soft PTFE grades in particular, smear and burr easily. Sharp new drills, appropriate feed and retract speeds and good entry and backup material are what produce a smooth wall without burrs, and none of them can be substituted by a slower drilling speed alone.
PTFE is non-porous and chemically inert, which makes hole wall activation difficult. Desmear, typically by plasma treatment, has to be thorough enough to give the wall the roughness and chemical activity that electroless copper needs to bond. When it is not, the copper deposits cleanly and separates later, which is one of the hardest faults to detect before it becomes a field failure.
The objective is a copper wall of even thickness with no voids or cracks. Holes that carry high current or have to meet high reliability requirements may need via filling instead of simple plating. Plating chemistry, current density and agitation all have to be controlled together, because varying any one of them alone simply moves the defect to a different location.
The last two stages decide whether the board that was built is the board that was designed. They also have more options than the earlier steps, which is why they need to be chosen rather than defaulted. The finish options and their trade-offs are compared in these steps and considerations for surface treatment in high-frequency production.
ENIG, electroplated nickel and gold, and immersion tin all protect the copper and all behave differently. ENIG gives a flat surface and good solderability but needs tight process control to avoid black pad, a hyper-corrosion of the nickel layer. Electroplated soft gold suits wire bonding. Immersion tin is economical but has a shorter shelf life. The right answer depends on the assembly method and the required storage life.
Controlled impedance lines should be measured by time domain reflectometry rather than assumed, and on critical products a vector network analyser is used to verify insertion loss and return loss directly. Reliability testing then takes over: thermal stress such as a solder dip at 288°C, thermal cycling, and highly accelerated temperature and humidity stress testing. These tests are what convert a passing prototype into a qualified product.
Every stage above has a characteristic failure mode, and most of them are visible in the finished board only as a symptom that points somewhere else. The table below maps the stage to the failure it produces and the control that prevents it, which is a faster route to a root cause than starting from the defect.
| Stage | Characteristic Failure | Control |
|---|---|---|
| Material selection | Phase distortion, higher attenuation than predicted | Uniform Dk across the panel, Df below 0.005, CTE matched to copper |
| Inner layer imaging | Impedance outside tolerance, reflection on controlled lines | Line width held within ±10%, undercut suppressed, low-profile foil |
| Lamination | Blistering, delamination, layer shift, uneven dielectric thickness | Clean lamination area, accurate registration, cycle developed per prepreg |
| Drilling | Smear and burrs on the hole wall, cracked barrels in deep holes | Sharp tooling, matched feed and retract speeds, correct entry and backup |
| Hole metallisation | Copper separating from the wall, voids in the plating | Thorough plasma desmear, controlled plating chemistry and current density |
| Surface finish | Black pad, poor solderability, extra insertion loss | Finish chosen for the assembly method; nickel layer controlled |
| Testing | Boards shipped outside impedance specification | TDR on controlled lines, VNA on critical products, thermal and humidity stress tests |
Multilayer high-frequency production is a chain, and its strength is set by the weakest link rather than by the best step. Material choice fixes what the board can do. Imaging and lamination fix whether it actually does it. Drilling and metallisation fix whether it keeps doing it. Testing is the only stage that tells you which of those three assumptions was wrong.
Where a decision has to be made early, it is usually the choice between laminated and assembled layer constructions, which changes the process chain rather than the parameters inside it; that comparison is set out in this article on laminated versus assembled high-frequency layers.
Frequently Asked Questions
Because it bonds every inner layer at once under heat and pressure, and the defects it produces are buried inside the finished board. Blisters, delamination, layer shift and uneven dielectric thickness all originate here, and none of them can be corrected afterwards.
A stable and uniform dielectric constant, a dissipation factor well below 0.005, thermal expansion matched to copper, and low moisture absorption. Uniformity matters as much as the absolute values, because variation across the panel causes phase distortion.
Typically within ±10% of the designed dimension, at feature sizes of 3/3 mil or finer. Impedance is a function of line width and dielectric thickness, so this tolerance is an electrical requirement rather than a cosmetic one.
Because it is non-porous and chemically inert, so electroless copper will not bond to the hole wall on its own. Desmear creates the roughness and chemical activity the plating needs; without it, the copper separates later in service.
Time domain reflectometry on controlled impedance lines, vector network analysis of insertion and return loss on critical products, and reliability testing that includes a solder dip at 288°C, thermal cycling and humidity stress testing.
Send us your stack-up, prepreg types and impedance requirements and we will confirm the lamination profile and registration control your build needs.
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