Stackup decisions sit upstream of everything: signal integrity, EMC, impedance control, power distribution. Yet a lot of designers pour their energy into routing, component placement and decoupling capacitors, and treat the stackup as a detail to settle later. That’s backwards — a poor stackup can turn an otherwise working design into an EMI nightmare.
One hardware engineer learned this the hard way. During a redesign, a six-layer board was cut down to four layers to save cost. Functional testing passed without a hitch — but EMC testing kept failing, with emissions running nearly 8 dB over Class B limits around 72 MHz. The root cause was the stackup: the power plane had been fragmented so heavily that return currents had to detour through the ground plane, forming loop antennas across the board.
A stackup influences three performance areas, and weakness in any one of them shows up in the finished product:
Every high-speed signal needs a nearby reference plane to give its return current a predictable path. Get that right and you:
The spacing between signal layers and their reference planes directly controls radiated emissions. Tighter spacing means:
Plane capacitance comes from the spacing between power and ground planes. More capacitance buys you:
Fall short in any of these areas and the whole board pays for it.
TOP → GND → POWER → BOTTOM
Still the most widely used four-layer arrangement, and for good reason — it’s cheap to make and hard to get wrong.
| Layer | Function |
|---|---|
| TOP | Signal routing |
| GND | Solid ground plane |
| POWER | Power plane |
| BOTTOM | Signal routing |
Keep the ground plane as continuous as you can. Power planes can be split into voltage islands, but heavy fragmentation disrupts return current paths — which is exactly what sank the six-to-four-layer redesign at the top of this article.
This variant makes sense when:
The trade-off is power integrity: a mixed signal/power layer usually loses reference-plane continuity.
Some designers use this to gain routing resources, but it creates real problems:
For modern high-speed digital or RF work, don’t.
One of the best cost-to-performance balances available:
The inner signal layer sits between two reference planes — a stripline structure that cuts radiated EMI dramatically.
More routing space, less reference-plane integrity. It suits:
Expect to spend extra time on spacing and crosstalk analysis.
Six layers cost more than four — but not as much more as most people assume. The manufacturing steps are largely identical; the extra cost is mostly prepreg and one more lamination cycle. Now weigh that against what staying at four layers forces on you:
Run those numbers and the six-layer board frequently wins on total cost.
The go-to stackup for:
The tight power–ground spacing also builds in real plane capacitance, which takes a lot of load off high-frequency decoupling.
Thickness is the other half of the stackup decision:
Advantages:
Drawbacks:
Increasingly common in embedded and consumer products.
Advantages:
Drawback:
The usual choice for RF systems, portable electronics and HDI boards.
Advantages:
Drawbacks:
Here’s the part that bites people late in a project: the stackup you pick determines the trace widths that impedance control demands. A 50Ω microstrip on a 1.6 mm board might need an 8 mil trace; the same 50Ω on a thinner stack might only need 4 mil.
This becomes critical at BGA fanout. If your BGA breakout needs 3.5 mil traces but the stackup demands 8 mil for impedance, the design is physically impossible — you have to change the stackup. Which is the whole point: plan the stackup before routing starts, not after.
The stackup is the foundation everything else sits on — signal integrity, EMC compliance, power integrity. Whether it’s a simple four-layer controller board or an eight-layer FPGA platform, getting the layer arrangement right early removes risk from the whole project. Structure, dielectric thickness, plane spacing and impedance targets deserve real decisions at the start of the design, not at the end.
Common questions about PCB stackup design — for project-specific review, contact our team directly.
TOP–GND–POWER–BOTTOM. It gives top-layer routing a solid ground reference, it's cheap to fabricate, and EMI performance is good as long as the ground plane stays continuous.
Two dedicated ground planes and an internal stripline signal layer. That means shorter return paths, lower EMI, tighter impedance control and better power distribution — and the difference shows up clearly in EMC testing.
When the design carries real high-speed traffic: FPGA banks, DDR4/DDR5, PCIe, SerDes and networking. Every signal layer gets its own reference plane, and the power–ground pair adds plane capacitance for free.
Yes. Thickness sets the dielectric spacing, and dielectric spacing sets the trace width needed to hit a target impedance — the same 50Ω can mean an 8 mil trace on 1.6 mm or roughly 4 mil on a thinner stack.
Breaking up the reference planes. Fragmented ground or power planes force return currents into long detours, and the resulting loops radiate — that's how a board that simulates fine fails EMC on the bench.
Send us your layer count, target impedance and key interfaces. Our engineering team will review the stackup, check manufacturability and quote your multilayer PCB.
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